Altera - EP1K50QC208-2N - FPGA for Price-Sensitive Low-Density Designs

EP1K50QC208-2N from Altera is a low-density applications to design sensitive and is now available from Farnell. Embedded high performance, building blocks of RAM dual-port RAM, ROM, or FIFO logic.

Vary from a low density of 576 to 4992 logic elements (ERP) and provide optimum performance and functionality to the effective implementation of low-cost, low density applications.

Pure 64-bit, 66 MHz Peripheral Component Interconnect (PCI) provides support to an important requirement in communication systems for high performance. Aceex devices have also locked loops (PLL) for clock management, including the Clock Lock function to I / O performance and functionality to improve the system clock Boost Clock multiply in the device Aceex 1K. Aceex 1K devices have also Volt Multi I / O operation, which enables them to communicate with devices operating at 5V, 3.3V and 2.5V, the devices use a low-cost packaging technologies, including Advanced FineLine BGA packages Same Frame the ability to migrate, the company said.