At Hot Chips, last week, AMD unveiled details about the upcoming 12-core "Magny-Cours" processor, which it hopes will help it remain competitive in the game server. In 2010, AMD 45 nm SOI, Magny-Cours uses the same basic Core micro architecture as the current Shanghai quad-processor database server, so if there is no improvement in performance by wire will come from better system design.
The idea of Magny-Cours is simple: Take two to six processors at the heart of Istanbul, they clock down a little on the power to reduce and work in a multi-chip module (MCM), so they can take in a socket. Using an MCA, AMD will be able to fit 12 cores in the same power envelope as heat and Istanbul.
Doing this work requires a little compromise, and one of them is the MCM itself. AMD had previously ridiculed for using an MCM first Intel dual-core effort, the Pentium 4-based Smithfield, not "true" dual-core. They repeated the charge in the first quad-core Intel, which is also an MCA. But with per-core Nehalem cleaning absolute performance, which AMD is eager to maintain a credible presence server, and part of that crowd is the determination of strategy of MCA who had mocked.
For reasons of system architecture, AMD MCM picture is somewhat more complicated than was Intel, Istanbul, because each chip has its own on-die dual-channel DDR3 memory controller, and four HyperTransport links. Obviously you can not support any full-chip interconnect bandwidth through a single connection, so AMD had to cut some ties.
The company has four overall MCM design HT 2.0 ports (two per chip) and four DDR3 memory ports (two per chip) on each MCM. For each chip, a link is x16 and one x8 is different. The two chips are connected in the module x16 link exc.
Even with four HT links and four memory channels for the MCM Fed to maintain the 12 cores is a lot to pack into an electrical outlet, bandwidth and hunger is a concern. To help alleviate the bandwidth pressure on AMD Istanbul assistance of a clever balance in the form of HT, and this assessment will be carried forward to Magny-Cours, where even more necessary.
One of the major challenges in the design of multiprocessor system is maintained caches of different processors in sync with the other solutions to this problem to a certain degree of communication between processors, and "snoop" bus traffic Dining the precious bandwidth. The solution adopted in Istanbul and Magny-Cours AMD involves the destruction of 6 MB of cache 1 MB per chip to store the contents of a directory caches of other chips, so by consulting the local telephone directory each chip can prevent a broadcaster major growing number of requests for traffic to snoop other chips.
The reason is that hormone Assist workspace is relatively cheap compared to tube and bus bandwidth, so that every trick you trade some transistors on die for a boost in bandwidth real world bus is a victory. In fact the basic idea behind all kinds of caches, and directory HT Assist is really just another type of cache. Bandwidth per socket will always be expensive if the number of cores in each socket increases, and so we see the plans multi swing back to the state of affairs at the end of the era single-core, ie where a transformer, which is usually a large proportion of very fast memory with a number of blocks to load attached.
After Magny-Cours, AMD plans to continue to raise the number of cores per socket, while maintaining backward compatibility with Magny-Cours and taken to Istanbul, power and thermals.
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